The present invention relates to semiconductor devices exhibiting reduced capacitance loading and to enabling methodology. The present invention has particular applicability in fabricating high density, multi-level semiconductor devices comprising sub-micron dimensions and exhibiting high circuit speed.
Interconnection technology is constantly challenged to satisfy the ever increasing requirements for high density and performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting production factor.
The dielectric constant of materials currently employed in fabricating semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one (1) for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9. One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 20(trademark) dielectric, a poly(arylene) ether, available from Allied Signal, Advanced Micromechanic Materials, Sunnvale, Calif., Black-Diamond(trademark) dielectric available from Applied Materials, Santa Clara, Calif., BCB (divinylsiloxane bis-benzocyclobutene) and Silk(trademark) dielectric, an organic polymer similar to BCB, both available from Dow Chemical Co., Midland, Mich. Other examples include porous, low density materials in which a significant fraction of the bulk volume contains air. The properties of these porous materials are proportional to their porosity, i.e., the greater the porosity, the less the dielectric constant.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tintanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein an ILD, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low-k material, is formed over an underlying metal level containing metal features, e.g., Cu or Cu alloy features with a silicon nitride capping layer. A damascene opening, e.g., via hole, trench, or dual damascene opening, is then formed in the ILD. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In attempting to implement Cu interconnects with low-k dielectric materials, such as porous low-k dielectric materials, several problems have been encountered. For example, in implementing dual damascene techniques, a silicon nitride middle-etch stop layer is employed. However, silicon nitride typically has a dielectric constant (k) of about 8.0 which is antithetic to the continuing drive for reduced capacitance. In addition, the etch stopping ability of silicon silicide is less than optimum An improvement in the etch selectivity of the middle-etch stop layer would increase manufacturing throughput and device reliability. In addition, it was found that the barrier layers typically deposited prior to Cu deposition exhibit poor wetting properties.
There exists a need for efficient methodology enabling the use of low-k dielectric materials, in fabricating high density, multi-level interconnection patterns based on Cu. There exists a particular need for such methodology enabling interconnect fabrication with reduced capacitance, improved middle-etch stop selectivity and improved barrier layer adhesion.
An advantage of the present invention is a semiconductor device having interconnect patterns exhibiting reduced parasitic Rxc3x97C time delays employing dielectric materials having a low dielectric constant.
Another advantage of the present invention is a method of manufacturing a semiconductor device having interconnect patterns exhibiting reduced parasitic Rxc3x97C time delays employing dielectric materials having a low dielectric constant with improved middle-etch stop selectivity and improved barrier layer adhesion.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a first dielectric layer over a conductive feature formed over a wafer; forming a graded middle-etch stop layer on the first dielectric layer, the graded middle-etch stop layer comprising: a first silicon carbide layer on the first dielectric layer; a silicon layer on the first silicon carbide layer; and a second silicon carbide layer on the silicon layer; forming a second dielectric layer on the graded middle-etch stop layer; forming a dual damascene opening comprising: an upper trench section in the second dielectric layer exposing the silicon layer at the bottom of the trench section; and a lower via hole section in the first dielectric layer exposing an upper surface of the conductive features; and filling the dual damascene opening with conductive material.
Another aspect of the present invention is a semiconductor device comprising: a first dielectric layer over a conductive feature; a graded middle-etch stop layer on the first dielectric layer, the graded middle-etch stop layer comprising: a first silicon carbide layer on the first dielectric layer; a silicon layer on the first silicon carbide layer; a second silicon carbide layer on the silicon layer; a second dielectric layer on the graded middle-etch stop layer; a dual damascene opening comprising: an upper trench section having side surfaces defined by the second dielectric layer and a bottom surface defined by the silicon layer; and a lower via hole section having side surfaces defined by the first dielectric layer and a bottom surface defined by an upper surface of the conductive feature; and conductive material filling the dual damascene opening.
Embodiments of the present invention comprise employing low-k dielectric materials, such as porous low-k dielectric materials as the first and second dielectric layers, and depositing the graded middle-etch stop layer by PECVD at a temperature of 300xc2x0 C. to 400xc2x0 C. Embodiments include depositing the first silicon carbide layer, employing TMS, He and NH3, at a thickness of 250 xc3x85 to 350 xc3x85, depositing the silicon layer on the first silicon carbide layer by PECVD employing SiH4, at a thickness of 20 xc3x85 to 50 xc3x85 and then depositing the second silicon carbide layer by PECVD employing TMS, He and NH3, at a thickness of 250 xc3x85 to 350 xc3x85. Embodiments of the present invention further include depositing a barrier layer, such as titanium or a composite comprising a layer of tantalum nitride with a layer of alpha-tantalum thereon. A seedlayer may then be deposited followed by filling the opening, as by electrodeposition or electrodeless deposition, with Cu. Chemical mechanical polishing (CMP) is then conducted to form a planarized upper surface, followed by deposition of a capping layer, such as silicon carbide or silicon nitride.